On-chip decoupling capacitance and P/G wire co-optimization for dynamic noise

被引:5
|
作者
Zhao, Min [1 ]
Panda, Rajendran [1 ]
Reschke, Ben [1 ]
Fu, Yuhong [1 ]
Mewett, Trudi [2 ]
Chandrasekaran, Sri [1 ]
Sundareswaran, Savithri [1 ]
Yan, Shu [1 ]
机构
[1] Freescale Semicond Inc, Austin, TX 78729 USA
[2] Australia Semicond Technol Comp Pty Ltd, Adelaide, SA 5000, Australia
关键词
decap; on-chip decoupling capacitance; wire enhancement; co-optimization; dynamic noise;
D O I
10.1109/DAC.2007.375145
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Decap allocation are the primary methods for addressing the dynamic voltage noise problem of on-chip power networks. When space in the immediate proximity of a hot spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation, we propose an efficient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10]. Experimental results on two actual chip designs demonstrate the area and run-time efficiency of the co-optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible solution.
引用
收藏
页码:162 / +
页数:2
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