The reliability issues on ASIC/memory integration by SiP (System-in-Package) technology

被引：0
|
作者：
Song, YH [1 ]
Kim, SG [1 ]
Rhee, KJ [1 ]
Cho, DS [1 ]
Kim, TS [1 ]
机构：
[1] SAMSUNG Elect Co Ltd, Syst LSI Div, Device Solut Network Business, ASIC Dev Team,ASIC Design PJ, Yongin, Kyunggi Do, South Korea
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
When integrating more than one chip in a package using so-called SiP (System-In-Package) technology, the size reduction rate is approximately 30similar to60% compared to the identical PCB (Printed Circuit Board). In this paper, we review the advantages of using SiP first, and then some of the reliability issues are discussed including leakage current, test, EMI (Electromagnetic Interference), EOS (Electrical Over Stress) and latch-up related to using SiP. Solutions to these reliabilities are proposed in this paper.
引用
收藏
页码：7 / 10
页数：4
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