Noise isolation modeling and experimental validation of power distribution network in chip-package

被引：0
|
作者：
Park, Hyunjeong [1 ]
Yoon, Changwook [1 ]
Koo, Kyoungchoul [1 ]
Kim, Joungho [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Taejon 305701, South Korea
来源：
2007 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY: WORKSHOP AND TUTORIAL NOTES, VOLS 1-3 | 2007年
关键词：
noise isolation; transfer impedance; power distribution network; measurement; chip and package;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper models the chip and the package power distribution network in the simplified SPICE-level. The model is successfully validated by experiments using Vector Network Analyzer. By using the SPICE-level model, the noise isolation between the noise current source at the chip and the power distribution network at the package is analyzed from 1MHz to 3GHz. The contribution of each part in the power distribution network is also analyzed by experiments. The transfer impedances are simulated and measured the power distribution network between the chip and the package varying with the wire-bond and the on-package decoupling capacitor, case by case.
引用
收藏
页码：270 / 275
页数：6
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