Technological and design constraints for multilevel flash memories

被引：0
|
作者：
Calligaro, C
Manstretta, A
Modelli, A
Torelli, G
机构：
来源：
ICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2 | 1996年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper discusses basic constraints for multilevel storage in Flash memories. Aspects such as programming algorithms, threshold voltage distribution, data retention, read disturbs, sense amplifier sensitivity and cell transconduttance spread are considered. Experimental results and design considerations are provided. Guidelines for the evaluation of multilevel storage feasibility are given. The feasibility of four-level storage with present technologies using a read voltage around 6 V is demonstrated.
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收藏
页码：1005 / 1008
页数：4
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