Area-effcient re-encoding scheme for NAND Flash Memory with multimode BCH Error correction

This paper presents a novel method to reduce the area of the Bose Chaudhuri Hocquenghen (BCH) multimode encoder based on a re-encoding scheme. Previous methods for multimode BCH use several linear-feedback shift registers (LFSR) cascaded in series to achieve area efficient encoder, but for longer BCH codes the critical path becomes an issue for high throughput. A new encoding scheme is proposed to reduce the critical path for long BCH code. Without sacrificing the latency, this method reduces the hardware complexity by reusing the same module for the encoder and the syndrome generator, which is the first stage of the BCH decoder. The experimental results show that, in the case of BCH (8191, 7983, 16), there are logic savings of 25% between the encoder and the syndrome generator, and the method provides a reconfigurable error correction capability (tsel).