TSV Manufacturing Yield and Hidden Costs for 3D IC Integration

被引：105
|
作者：
Lau, John H. [1 ]
机构：
[1] Ind Technol Res Inst, Elect & Optoelect Labs, Hsinchu 310, Taiwan
来源：
2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2010年
关键词：
THROUGH-SILICON VIAS; FILLED TSV; WAFER; INTERPOSER; SYSTEM; FABRICATION; TECHNOLOGY; DESIGN;
D O I：
10.1109/ECTC.2010.5490828
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general, the TSV (through-silicon-via) separates the 3D IC packaging and 3D IC/Si integrations, i.e., the latter two use TSV, but 3D IC packaging does not. TSV for 3D integration is >26 years old technology, which (with a new concept that every chip could have two active surfaces) is the focus of this study. Emphasis is placed on the TSV manufacturing yield and hidden costs. A 3D integration roadmap is also provided.
引用
收藏
页码：1031 / 1042
页数：12
相关论文
共 50 条
  • [31] 3D Copper TSV Integration, Testing and Reliability
    Farooq, M. G.
    Graves-Abe, T. L.
    Landers, W. F.
    Kothandaraman, C.
    Himmel, B. A.
    Andry, P. S.
    Tsang, C. K.
    Sprogis, E.
    Volant, R. P.
    Petrarca, K. S.
    Winstel, K. R.
    Safran, J. M.
    Sullivan, T. D.
    Chen, F.
    Shapiro, M. J.
    Hannon, R.
    Liptak, R.
    Berger, D.
    Iyer, S. S.
    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
  • [32] TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC
    Hung Viet Nguyen
    Ryu, Myunghwan
    Kim, Youngmin
    IEICE TRANSACTIONS ON ELECTRONICS, 2012, E95C (12): : 1864 - 1871
  • [33] Performance Characterization of TSV in 3D IC via Sensitivity Analysis
    You, Jhih-Wei
    Huang, Shi-Yu
    Kwai, Ding-Ming
    Chou, Yung-Fa
    Wu, Cheng-Wen
    2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010), 2010, : 389 - 394
  • [34] Electrical Analyses of TSV-RDL-Bump of Interposers for High-Speed 3D IC Integration
    Sung, Tseshih
    Chiang, Kevin
    Lee, Daniel
    Ma, Mike
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 865 - 870
  • [35] TSV-aware Scan Chain Reordering for 3D IC
    Datta, Ayan
    Nagarajan, Charudhattan
    Kolay, Susmita Sur
    2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, : 188 - 193
  • [36] TSV NOISE COUPLING IN 3D IC USING GUARD RING
    Reddy, R. Ranga
    Tanna, Sugandh
    Singh, Shiv Govind
    Singh, Om Krishna
    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015), 2015,
  • [37] A Thermal-Aware Distribution Method of TSV in 3D IC
    Hou, Ligang
    Fu, Jingyan
    Wang, Jinhui
    Gong, Na
    Zhao, Wei
    Geng, Shuqin
    PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
  • [38] TSV-Aware Analytical Placement for 3D IC Designs
    Hsu, Meng-Kai
    Chang, Yao-Wen
    Balabanov, Valeriy
    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 664 - 669
  • [39] 3D IC Integration Using Blockchain
    Radeep Krishna, R.
    Sivakumar, P.
    Abraham, C.G.
    Sreedivya, K.M.
    Lecture Notes in Networks and Systems, 2023, 540 : 317 - 344
  • [40] Mapping progress in 3D IC integration
    LoPiccolo, P
    SOLID STATE TECHNOLOGY, 2006, 49 (06) : 34 - +
12345