Programmable phase locked loops for digital signal processors

被引：0

作者：

Leonov, GA ^{[1
]}

Seledzhi, SM ^{[1
]}

机构：

[1] St Petersburg State Univ, Fac Math & Mech, St Petersburg 198504, Russia

来源：

2003 INTERNATIONAL CONFERENCE PHYSICS AND CONTROL, VOLS 1-4, PROCEEDINGS: VOL 1: PHYSICS AND CONTROL: GENERAL PROBLEMS AND APPLICATIONS; VOL 2: CONTROL OF OSCILLATIONS AND CHAOS; VOL 3: CONTROL OF MICROWORLD PROCESSES. NANO- AND FEMTOTECHNOLOGIES; VOL 4: NONLINEAR DYNAMICS AND CONTROL | 2003年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In systems of digital signal processors (array processors) the synchronization problems arise. In. these systems the clock skew may be significant and may lead to the incorrect work of parallel algorithms. A clock skew can fie eliminated by globally stable phase locked loops. Locally and globally stability of continuous and discrete phase locked loops for digital signal processors are considered The parameters of period doubling bifurcations for discrete. phase locked loop are obtained.

引用

页码：548 / 554

页数：7

共 50 条

[31] ONE APPROACH TO ANALYSIS OF DIGITAL PHASE LOCKED LOOPS
SHAKHTARIN, BI
ARKHANGE.VA
[J]. RADIOTEKHNIKA I ELEKTRONIKA, 1974, 19 (10): : 2197 - 2200
[32] IMPROVED DCO SCHEME FOR DIGITAL PHASE LOCKED LOOPS
SZYMANSKI, JW
[J]. ELECTRONIC ENGINEERING, 1977, 49 (589): : 24 - 25
[33] Smoothing the Way for Digital Phase-Locked Loops
Ho, Cheng-Ru
Chen, Mike Shuo-Wei
[J]. IEEE MICROWAVE MAGAZINE, 2019, 20 (05) : 80 - 97
[34] Phase-jitter dynamics of digital phase-locked loops
Teplinsky, A
Feely, O
Rogers, A
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1999, 46 (05): : 545 - 558
[35] CIRCUMVENTING BCD ADDITION IN DIGITAL PHASE-LOCKED LOOPS
MARTIN, L
[J]. ELECTRONICS, 1972, 45 (11): : 100 - &
[36] CLASS OF ALL DIGITAL PHASE LOCKED LOOPS - MODELING AND ANALYSIS
REDDY, CP
GUPTA, SC
[J]. IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, 1973, AES9 (05) : 812 - 812
[37] Stability Criteria for Classical Digital Phase-Locked Loops
Abu Bakar, Siti Juliana
Ahmad, Nur Syazreen
[J]. 9TH INTERNATIONAL CONFERENCE ON ROBOTIC, VISION, SIGNAL PROCESSING AND POWER APPLICATIONS: EMPOWERING RESEARCH AND INNOVATION, 2017, 398 : 427 - 433
[38] Digital phase-locked loops tracked by a relay sensor
INRIA Rocquencourt, Domaine de Voluceau, 78153 Le Chesnay cedex, France
不详
[J]. IEEE Trans Commun, 5 (667-669):
[39] NONLINEAR DYNAMICS OF DIGITAL PHASE-LOCKED LOOPS WITH DELAY
VIEIRA, MD
LICHTENBERG, AJ
LIEBERMAN, MA
[J]. INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS, 1994, 4 (03): : 715 - 726
[40] A MODEL FOR DIGITAL PHASE-LOCKED LOOPS AT LOW SNR
BENTAYEB, S
MARAL, G
[J]. ANNALES DES TELECOMMUNICATIONS-ANNALS OF TELECOMMUNICATIONS, 1986, 41 (3-4): : 133 - 146

← 1 2 3 4 5 →