Smoothing the Way for Digital Phase-Locked Loops

被引：4

作者：

Ho, Cheng-Ru ^{[1
]}

Chen, Mike Shuo-Wei ^{[2
]}

机构：

[1] Inphi Corp, Santa Clara, CA 95054 USA

[2] Univ Southern Calif, Ming Hsieh Dept, Los Angeles, CA USA

来源：

关键词：

FREQUENCY-SYNTHESIZER; FRACTIONAL SPUR; MITIGATION; TDC; PLL;

D O I：

10.1109/MMM.2019.2898022

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：80 / 97

页数：18

共 50 条

[1] Digital Phase-Locked Loops
Levantino, Salvatore
2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2018,
[2] DIGITAL PHASE-LOCKED LOOPS
不详
HEWLETT-PACKARD JOURNAL, 1987, 38 (10): : 15 - 15
[3] Advanced Digital Phase-Locked Loops
Levantino, Salvatore
2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013,
[4] ON OPTIMUM DIGITAL PHASE-LOCKED LOOPS
GUPTA, SC
IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1968, CO16 (02): : 340 - &
[5] A Digital BIST for Phase-Locked Loops
Sliech, Kevin
Margala, Martin
23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2008, : 134 - 142
[6] Chimeras in digital phase-locked loops
Paul, Bishwajit
Banerjee, Tanmoy
CHAOS, 2019, 29 (01)
[7] OPTIMUM DIGITAL PHASE-LOCKED LOOPS
RUDDELL, AJ
ROSIE, AM
ELECTRONICS LETTERS, 1975, 11 (18) : 440 - 441
[8] A SURVEY OF DIGITAL PHASE-LOCKED LOOPS
LINDSEY, WC
CHIE, CM
PROCEEDINGS OF THE IEEE, 1981, 69 (04) : 410 - 431
[9] Phase-locked loops
Bateman, C
ELECTRONICS WORLD, 2000, 106 (1769): : 392 - 395
[10] PHASE-LOCKED LOOPS
GUPTA, SC
PROCEEDINGS OF THE IEEE, 1975, 63 (02) : 291 - 306