Power/Ground supply network optimization for power-gating

Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects on power supply network, which have not been considered in the earlier design stages. Ignoring those effects may result in suboptimal power supply network designs an could potentially even nullify the intended power savings. In this paper, we analyze mutual dependencies between the sleep transistors and the P/G network, and we present a general flow to optimize the P/G supply network for power-gating. Experimental results show that sizing sleep transistor and power network separately cannot achieve optimal solution in terms of power. By compromising only 1% of the total area, our optimization method allows us to save 10% of power dissipated on decaps and sleep transistors, which is a practical solution for a power-gated system. We also report results of a study on optimal solutions for various gated areas and current densities.