A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS with Passive Residue Transfer

被引：0
|
作者：
Huang, Hai [1 ]
Du, Ling [1 ,2 ]
Chiu, Yun [1 ]
机构：
[1] Univ Texas Dallas, Analog & Mixed Signal Lab, Texas Analog Ctr Excellence, Richardson, TX 75080 USA
[2] Univ Elect Sci & Technol China, Chengdu, Sichuan, Peoples R China
来源：
2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2015年
关键词：
2b-1b/cycle; passive residue transfer; SAR ADC; two-step;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A hybrid 2b-1b/cycle, two-step asynchronous SAR ADC exploiting the passive residue transfer technique is reported in this paper. The removal of the residue amplifier results in much savings in the time and power consumed for the residue transfer process. Moreover, the 2b-1b/cycle conversion scheme assisted by the asynchronous time allocation during the bit cycles further enhances the conversion speed. Fabricated in a 65-nm CMOS process, the prototype ADC measured an SNDR of 43.7 dB and an SFDR of 58.1 dB for a near Nyquist input. The total power consumption of the ADC is 5.0 mW and the achieved FoM is 35 fJ/conversion-step, all measured at a sample rate of 1.2 GS/s.
引用
收藏
页码：221 / 224
页数：4
相关论文
共 50 条
  • [21] A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s Two-Step SAR ADC
    Hu, Yao-Sheng
    Huang, Po-Chao
    Yang, Mi-Ti
    Wu, Shih-Wei
    Chen, Hsin-Shu
    2016 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2016, : 81 - 84
  • [22] An 11-bit 500 MS/s Two-Step SAR ADC with Non-attenuated Passive Residue Transfer
    He, Wenbin
    Ye, Fan
    Ren, Junyan
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [23] An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS
    Yang, Xi
    Bae, Seung-Jun
    Lee, Hae-Seung
    IEEE 45TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC 2019), 2019, : 305 - 308
  • [24] A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS
    Zhu, Shuang
    Wu, Bo
    Cai, Yongda
    Chiu, Yun
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (04) : 1172 - 1183
  • [25] A 6-Bit, 1.2-GS/s ADC with Wideband THA in 0.13-μm CMOS
    Chen, Bo-Wei
    Hsien, Szu-Kang
    Chiang, Cheng-Shiang
    Juang, Kai-Cheung
    2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 377 - 380
  • [26] A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS
    Yang, Jing
    Naing, Thura Lin
    Brodersen, Bob
    PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2009, : 287 - 290
  • [27] A 6-bit 2 GS/s ADC in 65 nm CMOS
    WANG HaoNan
    WANG Tao
    YAO YuFeng
    WANG Hui
    CHENG YuHua
    ScienceChina(InformationSciences), 2014, 57 (06) : 294 - 298
  • [28] A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC
    Hu, Yao-Sheng
    Huang, Po-Chao
    Tai, Hung-Yen
    Chen, Hsin-Shu
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (12) : 1166 - 1170
  • [29] A 6-bit 2 GS/s ADC in 65 nm CMOS
    HaoNan Wang
    Tao Wang
    YuFeng Yao
    Hui Wang
    YuHua Cheng
    Science China Information Sciences, 2014, 57 : 1 - 5
  • [30] Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS
    Ferenci, Damir
    Groezing, Markus
    Berroth, Manfred
    PRIME: PROCEEDINGS OF THE CONFERENCE 2009 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, 2009, : 1 - 3
12345