A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS with Passive Residue Transfer

被引：0

作者：

Huang, Hai ^{[1
]}

Du, Ling ^{[1
,2
]}

Chiu, Yun ^{[1
]}

机构：

[1] Univ Texas Dallas, Analog & Mixed Signal Lab, Texas Analog Ctr Excellence, Richardson, TX 75080 USA

[2] Univ Elect Sci & Technol China, Chengdu, Sichuan, Peoples R China

来源：

2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2015年

关键词：

2b-1b/cycle; passive residue transfer; SAR ADC; two-step;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A hybrid 2b-1b/cycle, two-step asynchronous SAR ADC exploiting the passive residue transfer technique is reported in this paper. The removal of the residue amplifier results in much savings in the time and power consumed for the residue transfer process. Moreover, the 2b-1b/cycle conversion scheme assisted by the asynchronous time allocation during the bit cycles further enhances the conversion speed. Fabricated in a 65-nm CMOS process, the prototype ADC measured an SNDR of 43.7 dB and an SFDR of 58.1 dB for a near Nyquist input. The total power consumption of the ADC is 5.0 mW and the achieved FoM is 35 fJ/conversion-step, all measured at a sample rate of 1.2 GS/s.

引用

页码：221 / 224

页数：4

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