Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65nm-node high performance eDRAM

被引：33

作者：

Kajita, A ^{[1
]}

Usui, T ^{[1
]}

Yamada, M ^{[1
]}

Ogawa, E ^{[1
]}

Katata, T ^{[1
]}

Sakata, A ^{[1
]}

Miyajima, H ^{[1
]}

Kojima, A ^{[1
]}

Kanamura, R ^{[1
]}

Ohoka, Y ^{[1
]}

Kawashima, H ^{[1
]}

Tabuchi, K ^{[1
]}

Nagahata, K ^{[1
]}

Kato, Y ^{[1
]}

Hayashi, T ^{[1
]}

Kadomura, S ^{[1
]}

Shibata, H ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, SoC Res & Dev Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2003年

关键词：

D O I：

10.1109/IITC.2003.1219697

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

100nm half-pitch Cu dual-damascene (DD) interconnects with low-k hybrid (PAE(k2.65)/SiOC(k2.5)/SiC(k3.5)) dielectrics have been successfully integrated for a 65nm-node high performance embedded DRAM. The hybrid-DD structure was fabricated by applying a hard mask process combined with Stacked Mask Process (S-MAP). Well-controlled DD profile of the hybrid structure can provide the advantage of void-less Cu fill, resulting from over-hang reduction of PVD barrier metal. Stress-induced voiding (SiV), which is becoming a more serious problem with down scaling of via-hole dimension was found to be drastically improved as compared with homogeneous-DD structures. Thermal cycle test (TCT) also shows no degradation of the wiring/via-hole properties. Moreover, the result of electromigration (EM) test shows a tight distribution of mean time to failure (MTF). The hybrid-DD structure can extend the PVD Cu filling process to 65nm-node Cu metallization with excellent reliability.

引用

页码：9 / 11

页数：3

共 50 条

[21] RF Performance Boosting for 40nm-node CMOS Device by Low-k/Cu Dual Damascene Contact
Kawahara, J.
Hijioka, K.
Kume, I.
Nagase, H.
Tanabe, A.
Ueki, M.
Yamamoto, H.
Ito, F.
Inoue, N.
Tagami, M.
Furutake, N.
Onodera, T.
Saito, S.
Takeuchi, T.
Fukai, T.
Asada, M.
Arita, K.
Motoyama, K.
Nakajima, A.
Nakazawa, E.
Kitao, R.
Fujii, K.
Sekine, M.
Ikeda, M.
Hayashi, Y.
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, : 611 - +
[22] Reliability and conduction mechanism study on organic ultra low-k (k=2.2) for 65/45 nm hybrid Cu damascene technology
Su, YN
Shieh, JH
Perng, BC
Jang, SM
Liang, MS
PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 54 - 56
[23] Technology reliability qualification of a 65nm CMOS Cu/Low-k BEOL interconnect
Chen, F.
Li, B.
Lee, T.
Christiansen, C.
Gill, J.
Angyal, M.
Shinosky, M.
Burke, C.
Hasting, W.
Austin, R.
Sullivan, T.
Badami, D.
Aitken, J.
IPFA 2006: PROCEEDINGS OF THE 13TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2006, : 97 - +
[24] High Performance Cu/Low-k Interconnect Strategy beyond 10nm Logic Technology
Kim, R. -H.
Kim, B. H.
Kim, J. N.
Lee, J. J.
Baek, J. M.
Hwang, J. H.
Hwang, J.
Chang, J.
Yoo, S. Y.
Yim, T. -J.
Chung, K. -M.
Park, K. H.
Oszinda, T.
Kim, I. S.
Lee, E. B.
Nam, S. D.
Jung, S.
Cho, Y. W.
Choi, H. J.
Kim, J. S.
Ahn, S. H.
Park, S. H.
Yoon, B. U.
Ku, J. -H.
Paak, S. S.
Lee, N. -I.
Choi, S.
Kang, H. -K.
Jung, E. S.
2015 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE AND 2015 IEEE MATERIALS FOR ADVANCED METALLIZATION CONFERENCE (IITC/MAM), 2015, : 1 - 3
[25] Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node
Ikeda, A.
Travaly, Y.
Humbert, A.
Hoofman, R. J. O. M.
Li, Y. -L.
Tokei, Zs.
Iacopi, F.
Michelon, J.
Bruynseraede, C.
Willegems, M.
Hendrickx, D.
Van Aelst, J.
Struyf, H.
Versluijs, J.
Heylen, N.
Carbonell, L.
Richard, O.
Bender, H.
Kaiser, M.
Weemaes, R. G. R.
Verheyden, G.
Kemeling, N.
Fukazawa, A.
Matsuki, N.
Sprey, H.
Ciofi, I.
Beyer, G.
Van Hove, M.
PROCEEDINGS OF THE IEEE 2006 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2006, : 42 - +
[26] Highly Reliable and Low Resistive Cu/Low-k Dual Damascene Interconnects by Using TaTi Barrier Metal
Motoyama, K.
Fujii, K.
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2012, 1 (06) : P279 - P284
[27] Hybrid low-k/Cu dual damascene process for 45-32 nm technology node using self-assembled porous-silica ultra low-k films
Chikaki, S
Shimoyama, M
Yagi, R
Yoshino, T
Ono, T
Ishikawa, A
Fujii, N
Hata, N
Nakayama, T
Kohmura, K
Tanaka, H
Goto, T
Kawahara, J
Sonoda, Y
Matsuo, H
Seino, Y
Takada, S
Kunimi, N
Uchida, Y
Hishiya, S
Shishida, Y
Kinoshita, K
Kikkawa, T
PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 48 - 50
[28] Integration of Cu damascene with pore-sealed PECVD porogen low-k (k=2.5) dielectrics for 65nm generation
Yeh, M. L.
Chou, C. C.
Bao, T. I.
Lin, K. C.
Chen, I. I.
Huang, K. P.
Wu, Z. C.
Jeng, S. M.
Yu, C. H.
Liang, M. S.
2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 133 - +
[29] Reliability robustness of 65nm BEOL Cu damascene interconnects using porous CVD low-k dielectrics with k=2.2
Lin, KC
Lu, YC
Li, LP
Chen, BT
Chang, HL
Lu, HH
Jeng, SM
Jang, SM
Liang, MS
2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2004, : 66 - 67
[30] High performance 90/65nm BEOL technology with CVD porous low-k dielectrics (k∼2.5) and low-k etching stop (k∼3.0)
Wu, ZC
Chou, TJ
Lin, SH
Huang, YL
Lin, CH
Li, LP
Chen, BT
Lu, YC
Chiang, CC
Chen, MC
Chang, W
Jang, SM
Liang, MS
2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 849 - 852

← 1 2 3 4 5 →