LVDCSL: A high fan-in, high-performance, low-voltage differential current switch logic family

This paper presents a low voltage differential current switch logic (LVDCSL) gate capable of achieving high performance for large fan-in gates. High fan-in is enabled by using a large height predischarged N channel metal-oxide-semiconductor (NMOS) trees. The power penalty of an increased number of internal nodes in the gate is mitigated by restricting their voltage swings. The salient features of this low-voltage DCSL family are high speed for high fan-in large stack height NMOS trees, low power due to restricted internal voltage swings, simple interface to static complementary metal-oxide-semiconductor (CMOS), and a latching nature which locks out inputs once outputs are evaluated. Results show that LVDCSL is capable of working at under 2 V in a 0.35-mu CMOS process while being faster than comparable Domino gates. At the same time total power consumption is reduced. LVDCSL achieves 40% delay improvement and 22% power reduction in comparison with dual rail Domino gates for 8 bit carry look-ahead circuits. Results for the critical path of an adder reveal that the complexity afforded by the gate, effectively decreases the number of logic levels and leads to improved performance.