Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory

被引：7
|
作者：
Liu, Peng [1 ]
Wu, Jigang [1 ]
You, Zhiqiang [2 ]
Elimu, Michael [2 ]
Wang, Weizheng [3 ]
Cai, Shuo [3 ]
机构：
[1] Guangdong Univ Technol, Sch Comp, Guangzhou, Guangdong, Peoples R China
[2] Hunan Univ, Coll Comp Sci & Elect Engn, Changsha, Hunan, Peoples R China
[3] Changsha Univ Sci & Technol, Coll Comp & Commun Engn, Changsha, Hunan, Peoples R China
来源：
2018 IEEE 27TH ASIAN TEST SYMPOSIUM (ATS) | 2018年
基金：
中国国家自然科学基金;
关键词：
D O I：
10.1109/ATS.2018.00016
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption in 1R crossbars, is used as a large-scale memory system. In this paper, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers defined faults caused by electrical defects. The test time of the proposed test algorithm is reduced significantly compared with previous test algorithms that are enhanced for CMOL architecture.
引用
收藏
页码：25 / 29
页数：5
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