MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP

被引：0

作者：

Bohrn, Marek ^{[1
]}

Fujcik, Lukas ^{[1
]}

机构：

[1] Brno Univ Technol, Dept Microelect, Brno, Czech Republic

来源：

ICINCO 2009: PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON INFORMATICS IN CONTROL, AUTOMATION AND ROBOTICS, VOL 1: INTELLIGENT CONTROL SYSTEMS AND OPTIMIZATION | 2009年

关键词：

Artificial neural networks; Computation acceleration; FPGA; VHDL; Spartan-3;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article describes a design and features of a multi-core unit for performing computing operations required for artificial neural network functioning. Its purpose is to speed up computing operations of the neural network. The number of computing cores can be altered as needed to achieve the required performance. VHDL language has been used to build this module. It has been optimized for the Spartan-3 family FPGA chips from Xilinx. These chips are favorable because of their low price and a high number of on-chip multipliers and block memory units. Spartan-3 chips facilitate parallel computing operations within neural networks to a very high level and thus help to achieve high computing power.

引用

页码：149 / 152

页数：4

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