FPGA Verification for Heterogeneous Multi-Core Processor

被引：0
|
作者：
Li X. [1 ,2 ,3 ]
Tang Z. [1 ,2 ,3 ]
Li W. [3 ]
机构：
[1] State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing
[2] School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing
[3] Shanghai Processor Technology Innovation Center, Shanghai
来源：
Jisuanji Yanjiu yu Fazhan/Computer Research and Development | 2021年 / 58卷 / 12期
基金：
中国国家自然科学基金;
关键词：
Adaptive delay adjustment; Field programmable gate array (FPGA) prototyping; Heterogeneous multi-core; Inter-core replacement simulation; Speed bridge; Virtual logic analyzer (VLA);
D O I：
10.7544/issn1000-1239.2021.20200289
中图分类号：
学科分类号：
摘要：
With the development of processor architecture, high-performance heterogeneous multi-core processors are emerging. Since the design of high-performance heterogeneous multi-core processor is very complex, in order to reduce the design risk, shorten the verification cycle, carry out software development in advance, reproduce the post-silicon problems, we usually need to build a prototype verification platform of field programmable gate array (FPGA), and based on the FPGA platform to carry out a variety of software and hardware verification and debugging work with different functions. This paper presents a method of debugging and verifying heterogeneous multi-core high-performance processor based on homogeneous FPGA platform which effectively utilizes the architecture characteristics of heterogeneous multi-core processor and the symmetry characteristics of homogeneous FPGA platform, divides FPGA by hierarchical top down method, builds the platform from bottom to up. The combination of speed bridge, adaptive delay adjustment, embedded virtual logic analyzer and other technologies can quickly complete the FPGA platform bring-up and deployment. The proposed multi-core complementary, inter-core replacement simulation method with debug SHELL can verify the target high-performance heterogeneous multi-core processor quickly and completely. Through the FPGA prototyping platform, we have successfully completed the pre-silicon verification,software hardware co-development and testing, post-silicon bug reproduce and also provided a fast hardware platform for the next generation processor's architecture design. © 2021, Science Press. All right reserved.
引用
收藏
页码：2684 / 2695
页数：11
相关论文
共 15 条
  • [1] Guo Yang, Li Sikun, Qu Wanxia, Verification of on-chip multi-core processor: Challenges, status, forcasts, Journal of Computer-Aided Design and Computer Graphics, 24, 12, pp. 1521-1532, (2012)
  • [2] Evans A, Silburt A, Vrckovnik G, Et al., Functional verification of larger ASICs, Proc of the 35th Design Automation Conf, pp. 650-655, (1998)
  • [3] Beltrame G, Bolchini C, Fossati L, Et al., ReSP: A non-intrusive transaction-level reflective MPSoC simulation platform for design space exploration, Proc of 2008 Asia South Pacific Design Automation Conf, pp. 673-678, (2008)
  • [4] Ganapathy G, Narayan R, Jorden G, Et al., Hardware emulation for functional verification of K5, Proc of the 33rd Design Automation Conf, pp. 315-318, (1996)
  • [5] Zhang Heng, Shen Haihua, Function verification of Godson2 processor, Journal of Computer Research and Development, 43, 6, pp. 974-979, (2006)
  • [6] Gateley J, Blatt M, Chen D, Et al., UltraSPARC-I emulation, Proc of the 32nd ACM/IEEE Design Automation Conf, pp. 13-18, (1995)
  • [7] Ray J, Hoe J C., High-level modeling and FPGA prototyping of microprocessors, Proc of the 11th ACM/SIGDA Int Symp on Field Programmable Gate Arrays(FPGA 03), pp. 100-107, (2003)
  • [8] Gschwind M, Salapura V, Maurer D., FPGA prototyping of a RISC processor core for embedded applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9, 2, pp. 241-250, (2001)
  • [9] Roland E, Wunderlich, Hoe J C., In-system FPGA prototyping of an Itanium microarchitecture, Proc of IEEE Int Conf on Computer Design (ICCD'04), pp. 288-194, (2004)
  • [10] Lu S, Yiannacouras P, Kassa R, Et al., An FPGA-based Pentium in a complete desktop system, Proc of the 15th ACM/SIGDA Int Symp on Field Programmable Gate Arrays (FPGA'07), pp. 53-59, (2007)
12