Quantitative Reliability Prediction Model for Wafer Level Packages under Board-Level Temperature Cycling

被引：0
|
作者：
Yang, Hung-Chun [1 ]
Kao, Chin-Li [2 ]
Chiu, Tz-Cheng [1 ]
Lee, Chang-Chi [2 ]
Hung, Sung-Ching [2 ]
Hung, Chih-Pin [2 ]
机构：
[1] Natl Cheng Kung Univ, 1 Univ Rd, Tainan 701, Taiwan
[2] ASE Grp, Kaohsiung 811, Taiwan
来源：
2014 9TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT) | 2014年
关键词：
DESIGN; WLCSP; CREEP;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A damage accumulation based interconnect fatigue failure model is developed for predicting the board-level temperature cycling (T/C) reliability of wafer level packages (WLPs). Creep and constant strain rate experiments were first performed to characterize the viscoplastic constitutive behavior of Pb-free solder. Finite element (FE) analyses based on the viscoplastic models were conducted for estimating inelastic strain energy density accumulation. The numerical results were then compared to a library of board-level T/C reliability test results for best fitting the reliability model. Factors such as alloy Ag content, package geometry, and ball grid array (BGA) layout are considered in the model.
引用
收藏
页码：325 / 328
页数：4
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