Quantitative Reliability Prediction Model for Wafer Level Packages under Board-Level Temperature Cycling

被引：0
|
作者：
Yang, Hung-Chun [1 ]
Kao, Chin-Li [2 ]
Chiu, Tz-Cheng [1 ]
Lee, Chang-Chi [2 ]
Hung, Sung-Ching [2 ]
Hung, Chih-Pin [2 ]
机构：
[1] Natl Cheng Kung Univ, 1 Univ Rd, Tainan 701, Taiwan
[2] ASE Grp, Kaohsiung 811, Taiwan
来源：
2014 9TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT) | 2014年
关键词：
DESIGN; WLCSP; CREEP;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A damage accumulation based interconnect fatigue failure model is developed for predicting the board-level temperature cycling (T/C) reliability of wafer level packages (WLPs). Creep and constant strain rate experiments were first performed to characterize the viscoplastic constitutive behavior of Pb-free solder. Finite element (FE) analyses based on the viscoplastic models were conducted for estimating inelastic strain energy density accumulation. The numerical results were then compared to a library of board-level T/C reliability test results for best fitting the reliability model. Factors such as alloy Ag content, package geometry, and ball grid array (BGA) layout are considered in the model.
引用
收藏
页码：325 / 328
页数：4
相关论文
共 50 条
  • [1] Investigations of board-level drop reliability of wafer-level chip-scale packages
    Lai, Yi-Shao
    Yeh, Chang-Lin
    Wang, Ching-Chun
    JOURNAL OF ELECTRONIC PACKAGING, 2007, 129 (01) : 105 - 108
  • [2] SACQ Solder Board Level Reliability Evaluation and Life Prediction Model for Wafer Level Packages
    Lin, Wei
    Pham, Quan
    Baloglu, Bora
    Johnson, Michael
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 1058 - 1064
  • [3] Prediction of board-level reliability of chip-scale packages under consecutive drops
    Yeh, CL
    Lai, YS
    Kao, CL
    PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 73 - 80
  • [4] Low Stress Dielectric Layers for Wafer Level Packages to Reduce Wafer Warpage and Improve Board-Level Temperature-Cycle Reliability
    Huneke, James T.
    Tay, SwecTeck
    PROCEEDINGS OF THE 2016 IEEE 18TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2016, : 176 - 180
  • [5] Evaluation of board-level reliability of electronic packages under consecutive drops
    Yeh, Chang-Lin
    Lai, Yi-Shao
    Kao, Chin-Li
    MICROELECTRONICS RELIABILITY, 2006, 46 (07) : 1172 - 1182
  • [6] Board-Level Reliability Performance of Discrete Power Packages
    Liu, Yumin
    Ian Almagro, Erwin
    Liu, Yong
    Jeon, O. S.
    Teysseyre, Jerome
    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, : 257 - 263
  • [7] Structural design optimization for board-level drop reliability of wafer-level chip-scale packages
    Tsai, Tsung-Yueh
    Lai, Yi-Shao
    Yeh, Chang-Lin
    Chen, Rong-Sheng
    MICROELECTRONICS RELIABILITY, 2008, 48 (05) : 757 - 762
  • [8] Optimal design towards enhancement of board-level thermomechanical reliability of wafer-level chip-scale packages
    Lai, Yi-Shao
    Wang, Tong Hong
    MICROELECTRONICS RELIABILITY, 2007, 47 (01) : 104 - 110
  • [9] Viscoelastic Influence on the Board Level Assessment of Wafer Level Packages Under Drop Impact and Under Thermal Cycling
    Misrak, Abel
    Bhandari, Rabin
    Agonafer, Dereje
    JOURNAL OF ELECTRONIC PACKAGING, 2023, 145 (01)
  • [10] Underfilled BGAs for ceramic BGA packages and board-level reliability
    Burnette, T
    Johnson, Z
    Koschmieder, T
    Oyler, W
    50TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 2000 PROCEEDINGS, 2000, : 1221 - 1226
12345