Application of Convolutional Neural Networks to Regenerate Deterministic Test Patterns for BIST

被引:0
|
作者
Inamoto, Tsutomu [1 ]
Higami, Yoshinobu [1 ]
机构
[1] Ehime Univ, Grad Sch Sci & Engn, Matsuyama, Ehime, Japan
关键词
combinational circuit; fault detection; logic BIST; test pattern; artificial neural network;
D O I
10.1109/itc-cscc.2019.8793374
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This study displays preliminary results on a simple technique to improve fault coverages in the BIST technology. The technique assumes that a circuit which implements an ANN can be used with the target circuit, and effective test patterns are given beforehand. Such ANN circuit is utilized as a degraded memory which approximately regenerates given test patterns. In computational illustrations, fault coverages of test patterns by the technique are calculated on c7552 of the ISCAS'85 benchmark.
引用
收藏
页码:114 / 115
页数:2
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