A practical approach for efficiently extracting interconnect capacitances with floating dummy fills

We present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances for system-on-chip (SoC) designs. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy metal fills on the parasitic capacitance, signal delay, and crosstalk noise. Moreover, we address that interlayer dummy metal fills have more significant influences than intralayer ones in terms of the impact on coupling capacitances. When dummy metal fills are ignored, the error of capacitance extraction can be more than 30%, whereas the error of the proposed method is less than about 10% for many practical geometries. We also demonstrate, by comparison with capacitance results measured for a 90-nm test chip, that the error of the proposed method is less than 8%.