Multi-gate CMOS with fin-channel structures beyond planar CMOS scaling limits

被引：0
|
作者：
Hisamoto, D [1 ]
机构：
[1] Hitachi Ltd, Cent Res Lab, Tokyo 1858601, Japan
来源：
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A great deal of attention has been paid to FD-SOI and multi-gate devices because they show promise in overcoming device scaling limits. Here, many reported types of fin-channel devices are reviewed regarding their potential as technology boosters for post-CMOS scaling. This paper demonstrates that double-, triple-, and quadruple-gates have different advantages. Therefore, the device structure should be individually designed accordingly for specific applications.
引用
收藏
页码：96 / 99
页数：4
相关论文
共 39 条
  • [31] Full-quantum simulation of heterojunction TFET inverters providing better performance than multi-gate CMOS at sub-0.35V VDD
    Baravelli, E.
    Gnani, E.
    Gnudi, A.
    Reggiani, S.
    Baccarani, G.
    2013 THIRD BERKELEY SYMPOSIUM ON ENERGY EFFICIENT ELECTRONIC SYSTEMS (E3S), 2013,
  • [32] Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.
    Mathew, L
    Sadd, M
    Kalpat, S
    Zavala, M
    Stephens, T
    Mora, R
    Bagchi, S
    Parker, C
    Vasek, J
    Sing, D
    Shimer, R
    Prabhu, L
    Workman, GO
    Ablen, G
    Shi, Z
    Saenz, J
    Min, B
    Burnett, D
    Nguyen, BY
    Mogab, J
    Chowdhury, MM
    Zhang, W
    Fossum, JG
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 731 - 734
  • [33] From the Present to the Future: Scaling of Planar VLSI-CMOS Devices Towards 3D-FinFETs and Beyond 10nm CMOS Technologies; Manufacturing Challenges and Future Technology Concepts
    Hoentschel, Jan
    Wei, A.
    2015 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE, 2015,
  • [34] Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology
    Veloso, Anabela
    Chew, Soon Aik
    Higuchi, Yuichi
    Ragnarsson, Lars- Ake
    Simoen, Eddy
    Schram, Tom
    Witters, Thomas
    Van Ammel, Annemie
    Dekkers, Harold
    Tielens, Hilde
    Devriendt, Katia
    Heylen, Nancy
    Sebaai, Farid
    Brus, Stephan
    Favia, Paola
    Geypen, Jef
    Bender, Hugo
    Phatak, Anup
    Chen, Michael S.
    Lu, Xinliang
    Ganguli, Seshadri
    Lei, Yu
    Tang, Wei
    Fu, Xinyu
    Gandikota, Srinivas
    Noori, Atif
    Brand, Adam
    Yoshida, Naomi
    Thean, Aaron
    Horiguchi, Naoto
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 52 (04)
  • [35] Issues on Interfacial Oxide Layer (IL) in EOT Scaling of High-k/Metal Gate CMOS for 22nm Technology Node and Beyond
    Park, C. S.
    Kirsch, P. D.
    PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 8, 2010, 33 (03): : 45 - 52
  • [36] A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
    von Arnim, K.
    Augendre, E.
    Pacha, C.
    Schulz, T.
    San, K. T.
    Bauer, F.
    Nackaerts, A.
    Rooyackers, R.
    Vandeweyer, T.
    Degroote, B.
    Collaert, N.
    Dixit, A.
    Singanamalla, R.
    Xiong, W.
    Marshall, A.
    Cleavelin, C. R.
    Schruefer, K.
    Jurczak, M.
    2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 106 - +
  • [37] Circuit and Process Co-Design with Vertical Gate-All-Around Nanowire FET Technology to Extend CMOS Scaling for 5nm and Beyond Technologies
    Bao, T. Huynh
    Yakimets, D.
    Ryckaert, J.
    Ciofi, I.
    Baert, R.
    Veloso, A.
    Boemmels, J.
    Collaert, N.
    Roussel, P.
    Demuynck, S.
    Raghavan, P.
    Mercha, A.
    Tokei, Z.
    Verkest, D.
    Thean, A. V-Y.
    Wambacq, P.
    PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014), 2014, : 102 - 105
  • [38] Simulation and Comparative Study of Propagation Delay in Multi-Channel Quantum SWS-CMOS-Based Inverters Using II-VI Gate Insulator
    Almalki, A.
    Saman, B.
    Gudlavalleti, R.H.
    Chandy, J.
    Heller, E.
    Jain, F.C.
    International Journal of High Speed Electronics and Systems, 2024, 33 (2-3)
  • [39] Sub-25nm single-metal gate CMOS Multi-Bridge-Channel MOSFET (MBCFET) for high performance and low power application
    Lee, SY
    Yoon, EJ
    Shin, DS
    Kim, SM
    Suk, SD
    Kim, MS
    Kim, DW
    Park, D
    Kim, K
    Ryu, BI
    2005 Symposium on VLSI Technology, Digest of Technical Papers, 2005, : 154 - 155
1234