A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

被引：47

作者：

von Arnim, K. ^{[1
]}

Augendre, E. ^{[3
]}

Pacha, C. ^{[2
]}

Schulz, T. ^{[1
]}

San, K. T. ^{[3
,4
]}

Bauer, F. ^{[2
]}

Nackaerts, A. ^{[3
]}

Rooyackers, R. ^{[3
]}

Vandeweyer, T. ^{[3
]}

Degroote, B. ^{[3
]}

Collaert, N. ^{[3
]}

Dixit, A. ^{[3
]}

Singanamalla, R. ^{[3
]}

Xiong, W. ^{[4
]}

Marshall, A. ^{[4
]}

Cleavelin, C. R. ^{[4
]}

Schruefer, K. ^{[2
]}

Jurczak, M. ^{[3
]}

机构：

[1] Infineon Technol Leuven, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Infineon Technol, Munich, Germany

[3] IMEC, Leuven, Belgium

[4] Texas Instruments Inc, Dallas, TX USA

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339745

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undoped fins show an inverter delay of 13.9ps at 1 v the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to balk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability,for large-scale integration.

引用

页码：106 / +

页数：2

共 4 条

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