CMOS building block for Smart-Power Integrated Circuits

被引：0
|
作者：
dosReis, CA
Santiago, AS
机构：
来源：
ICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2 | 1996年
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暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes an integrated circuit, which is suitable for use as a building block in the design of Smart-Power Integrated Circuits. The circuit comprises a logic unit and an analog section that includes a Zero-Crossing Detector, two Linear-Ramp Generators and two Voltage Comparators. It produces several control pulses within the period of a sinewave input signal, allowing its use in a wide range of power-control circuits. Prototypes were implemented in CMOS, 1.2 mu m, n-Well technology. Experimental results from measured samples are presented.
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页码：892 / 895
页数：4
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