Techniques for reduced power and increased speed in dynamic and ratio logic circuits

被引：0
|
作者：
Kartschoke, P
Rohrer, N
机构：
来源：
PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 1996年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes three techniques for increasing the usefulness of dynamic and ratio logic circuits. The first allows the power of pre-discharged ratio logic circuits to be significantly reduced. The second approach improves the speed of a dynamic and ratio logic circuit by partitioning the common heavily loaded node. Finally, a circuit approach is disclosed that implements a low threshold NFET to improve the speed of a dynamic circuit. Each technique demonstrates the use of a heavily loaded dynamic or ratioed logic NOR gate.
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页码：175 / 178
页数：4
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