What's Cool for the Future of Ultra Low Power Designs?

被引：0

作者：

Nagaraj, N. S. ^{[1
]}

Byler, John ^{[2
]}

Nazifi, Koorosh ^{[3
]}

Puvvada, Venugopal ^{[4
]}

Saito, Toshiyuki ^{[5
]}

Gibbons, Alan ^{[6
]}

Balajee, S. ^{[7
]}

机构：

[1] Texas Instruments Inc, Dallas, TX 75243 USA

[2] Portland State Univ, Portland, OR 97207 USA

[3] Cadence Design Syst Inc, San Jose, CA USA

[4] Qualcomm India Pvt Ltd, Bangalore, Karnataka, India

[5] Renesas Elect Corp, Kawasaki, Kanagawa, Japan

[6] Synopsys Inc, Reading, Berks, England

[7] Texas Instruments India Pvt Ltd, Bangalore, Karnataka, India

来源：

PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE | 2010年

关键词：

System Level Power; System Design; Low Power;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Ultra low power and energy efficiency requirements are common to most IC designs today. Requirements range from extending battery life to operating on harvested energy, with applications ranging from consumer electronics to medical applications. Design methodologies have evolved over the past decade to cater to low power designs. This panel will discuss the design methodology challenges in the next generation ultra low power and energy efficient IC designs, covering EDA roadmap, low power standards, and design and verification flows.

引用

页码：523 / 524

页数：2

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