Design and Performance Analysis of High Electron Mobility Transistor Based Static Random Access Memory Cell for High Frequency Applications

This paper proposes a high performance HEMT based Static Random Access Memory (SRAM) cell. The work has been carried out to design HEMT based SRAM cell and analysis of performance matrix with various frequencies. Read delay and write delay have been also calculated for SRAM cell. The proposed HEMT based SRAM cell design compared and with repowered data for the validation of design approach. Based on the analysis of SRAM cell, read delay for 5 GHZ, 20 GHZ and 50 GHZ was 38.82 ps, 46.41 ps and 74.83 ps respectively. The write delay was 9.82 ps, 15.55 ps and 23.09 ps and the Static Noise Margin (SNM) was 355 mV, 310 mV and 245 mV. The design and analysis of HEMT SRAM cell was done using SILVACO TCAD tool in ALTAS Mixed mode simulator.