A 60 GHz-Standard Compatible Programmable 50 GHz Phase-Locked Loop in 90 nm CMOS

被引：12

作者：

Barale, F. ^{[1
]}

Sen, P. ^{[1
]}

Sarkar, S. ^{[1
]}

Pinel, S. ^{[1
]}

Laskar, J. ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30308 USA

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2010年 / 20卷 / 07期

关键词：

CMOS integrated circuits; frequency divider; millimeter-wave circuits; phase-locked loop (PLL);

D O I：

10.1109/LMWC.2010.2049444

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents, for the first time, a 60 GHz four-channel standard compatible heterodyne frequency synthesizer solution with low-cost reference signal. The presented PLL features a dual-core varactor-based LC cross-coupled voltage-controlled oscillator (VCO). The measured phase noise is -80.1 dBc/Hz at 1 MHz offset, and it is limited by the phase noise of the reference signal. The measured output spectrum shows spur suppression higher than 32 dBc. Using the lowest reference frequency to date (27 MHz), the presented PLL is suitable for applications in low cost fully integrated multi-gigabit 60 GHz CMOS radio transceivers.

引用

页码：411 / 413

页数：3

共 50 条

[1] A 5 GHz 90-nm CMOS all digital phase-locked loop
Lu, Ping
Sjoland, Henrik
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2011, 66 (01) : 49 - 59
[2] A 5 GHz 90-nm CMOS all digital phase-locked loop
Ping Lu
Henrik Sjöland
[J]. Analog Integrated Circuits and Signal Processing, 2011, 66 : 49 - 59
[3] A 75-GHz phase-locked loop in 90-nm CMOS technology
Lee, Jri
Liu, Mingchung
Wang, Huaide
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (06) : 1414 - 1426
[4] A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS
Hoshino, Hiroaki
Tachibana, Ryoichi
Mitomo, Toshiya
Ono, Naoko
Yoshihara, Yoshiaki
Fujimoto, Ryuichi
[J]. ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, : 472 - +
[5] 77 GHz Phase-Locked Loop for Automobile Radar System in 90 nm CMOS Technology
Lin, Yo-Sheng
Lan, Kai-Siang
Lin, Hsin-Chen
Lin, Yun-Wen
[J]. 2018 IEEE RADIO & WIRELESS SYMPOSIUM (RWS), 2018, : 220 - 223
[6] A 5GHz 90-nm CMOS All Digital Phase-Locked Loop
Lu, Ping
Sjoland, Henrik
[J]. 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2009, : 65 - 68
[7] A LOW-POWER 802.11 AD COMPATIBLE 60-GHZ PHASE-LOCKED LOOP IN 65-NM CMOS
Cheema, Hammad M.
Arsalan, Muhammad
Salama, Khaled N.
Shamim, Atif
[J]. MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2015, 57 (03) : 660 - 667
[8] 77 GHz phase-locked loop for automobile radar system in 90-nm CMOS technology
Lin, Yo-Sheng
Lan, Kai-Siang
Wang, Chien-Chin
Lin, Hsin-Chen
[J]. MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2018, 60 (03) : 546 - 555
[9] A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS
Lin, Bo-Yu
Liu, Shen-Iuan
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58 (10) : 617 - 621
[10] A 50-GHz phase-locked loop in 0.13-μm CMOS
Cao, Changhua
Ding, Yanping
Kenneth, K. O.
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (08) : 1649 - 1656

← 1 2 3 4 5 →