A synthesis methodology for AMS/RF circuit reliability: Application to a DCO design

被引:0
|
作者
Ferreira, Pietro Maris [1 ]
Petit, Herve [1 ]
Naviner, Jean-Francois [1 ]
机构
[1] ParisTech, CNRS LTCI, TELECOM ParisTech, Inst TELECOM, F-75634 Paris 13, France
关键词
CMOS; DEGRADATION; SIMULATION; ANALOG;
D O I
10.1016/j.microrel.2010.11.002
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Circuit ageing degradation is becoming worse in advanced technologies, while application fields like military, medical and energy demand more reliability. Thus, reliability is one of the most important challenges of the semiconductor industry [1]. In this work, we review the physical ageing phenomena, their simulation model, and how they can be avoided. Then, we propose a synthesis methodology composed of classical circuit optimization with the reliability analysis in earlier stages. Also, the variability of the integration process technology is taken into account. We compare a classical and a reliable designed digital controlled oscillator (DCO) in order to show a reduction of 16% in the oscillation frequency ageing degradation. In this way, the reliable design makes the circuit lifetime five times longer, if we fix the maximum frequency ageing degradation at 2.0%. Finally, we present the reliability as a design criterion, advantages and disadvantages of our methodology. (C) 2010 Elsevier Ltd. All rights reserved.
引用
收藏
页码:765 / 772
页数:8
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