Design and Analysis of New Ultra Low Power CMOS Based Flip-Flop Approaches

被引:2
|
作者
Jangam, Naga Raju [1 ]
Guthikinda, Likhitha [1 ]
Ramesh, G. P. [2 ]
机构
[1] MLR Inst Technol, Dept Elect & Commun, Hyderabad, India
[2] St Peters Inst Higher Educ & Res, Chennai 600054, Tamil Nadu, India
关键词
Adiabatic flip flops; Complementary metal oxide semiconductor; Pull up; Pull down networks; Power dissipation; Time delay; Very large-scale integration;
D O I
10.1007/978-981-19-2281-7_28
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The flip flops are essential part of the clocking circuits in complementary metal oxide semiconductor circuit based designs. The adiabatic flip flops are more useful in digital systems for clock switching applications. The clock switching approach with energy restoration is most popular and prominent for reducing power dissipation in ultra-low power based digital system designs. These flip flops playing key role in the design of energy efficient adiabatic clock switching methods and these flip flops works on the basis of adiabatic principle. In this research paper, we have simulated and analyzed the behavior of energy restoration flip flops. These are observed as one end condition capture and differential condition capture flip flops. Both the flip- flops are more useful in energy recovery methods. For better enhance results, we can use clock gate switching method together with energy restoration method. These are verified using cadence 180, 90 nm library technologies. Finally, we obtained desired results after simulation.
引用
收藏
页码:295 / 302
页数:8
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