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- [21] Practical atomistic dopant diffusion simulation of shallow junction fabrication processes and intrinsic fluctuations for sub-100nm MOSFETs NANOTECH 2003, VOL 2, 2003, : 125 - 128
- [23] CPL mask technology for sub-100nm contact hole imaging PHOTOMASK AND NEXT GENERATION LITHOGRAPHY MASK TECHNOLOGY XI, 2004, 5446 : 624 - 631
- [25] In-situ steam generation for shallow trench isolation in sub-100nm devices 11TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED THERMAL PROCESSING OF SEMICONDUCTORS, 2003, : 163 - 166
- [26] Circuit-level techniques to control gate leakage for sub-100nm CMOS ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2002, : 60 - 63
- [27] Design of analog subthreshold encoded neural network circuit in sub-100nm CMOS 2015 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN), 2015,
- [28] Advanced model and analysis for series resistance in sub-100nm CMOS including poly depletion and overlap doping gradient effect INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 723 - 726
- [29] The challenges in achieving sub-100nm MOSFETs SECOND ANNUAL IEEE INTERNATIONAL CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON, 1997 PROCEEDINGS, 1997, : 52 - 60
- [30] Defect inpsection and repair reticle (DIRRT) design for the 100nm and sub-100nm technology nodes 18TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS, 2002, 4764 : 244 - 253