High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability

被引:4
|
作者
Ochiai, K [1 ]
Iwasaki, H [1 ]
Naganuma, J [1 ]
Endo, M [1 ]
Ogura, T [1 ]
机构
[1] NTT, Human Interface Labs, Yokosuka, Kanagawa 2390847, Japan
关键词
D O I
10.1109/DATE.1999.761138
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability. The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final embedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software.
引用
收藏
页码:303 / 308
页数:6
相关论文
共 34 条
  • [1] Single-chip MPEG-2 video encoder
    Endo, Makoto
    Ogura, Takeshi
    Minami, Toshihiro
    Nitta, Koyo
    [J]. NTT R and D, 2000, 49 (11): : 618 - 626
  • [2] Block processing unit in a single-chip MPEG-2 video encoder LSI
    System ASIC Division, NEC Corporation, 1753, Shimonumabe, Nakahara-ku, Kawasaki, 211-8666, Japan
    不详
    不详
    不详
    不详
    不详
    不详
    [J]. J VLSI Signal Process Syst Signal Image Video Technol, 1 (59-64):
  • [3] A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI
    Yoichi Katayama
    Toshiaki Kitsuki
    Yasushi Ooi
    [J]. Journal of VLSI signal processing systems for signal, image and video technology, 1999, 22 : 59 - 64
  • [4] A block processing unit in a single-chip MPEG-2 video encoder LSI
    Katayama, Y
    Kitsuki, T
    Ooi, Y
    [J]. SIPS 97 - 1997 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION, 1997, : 459 - 468
  • [5] A block processing unit in a single-chip MPEG-2 video encoder LSI
    Katayama, Y
    Kitsuki, T
    Ooi, Y
    [J]. JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1999, 22 (01): : 59 - 64
  • [6] A software-based real-time MPEG-2 video encoder
    McVeigh, J
    Chen, GK
    Goldstein, J
    Gupta, A
    Keith, M
    Wood, S
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2000, 10 (07) : 1178 - 1184
  • [7] A complexity-scalable software-based MPEG-2 video encoder
    陈国斌
    陆新宁
    王兴国
    刘济林
    [J]. Journal of Zhejiang University-Science A(Applied Physics & Engineering), 2004, (05) : 75 - 81
  • [8] Complexity-scalable software-based MPEG-2 video encoder
    Chen G.-B.
    Lu X.-N.
    Wang X.-G.
    Liu J.-L.
    [J]. Journal of Zhejiang University-SCIENCE A, 2004, 5 (5): : 572 - 578
  • [9] An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture
    Ikeda, M
    Kondo, T
    Nitta, K
    Suguri, K
    Yoshitome, T
    Minami, T
    Naganuma, J
    Ogura, T
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS, 1999, : 44 - 50
  • [10] Performance of software-based MPEG-2 video encoder on parallel and distributed systems
    Akramullah, SM
    Ahmad, I
    Liou, ML
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1997, 7 (04) : 687 - 695