622-Mbit/s burst-mode clock and data recovery circuit with duty control in a jitter reduction circuit

被引：0
|
作者：
Park, CS
Lee, CG
Park, CS
机构：
[1] GIST, Dept Informat & Commun, Kwangju 500712, South Korea
[2] KOPTI, Photon Syst Lab, Kwangju 500210, South Korea
来源：
OPTICAL ENGINEERING | 2005年 / 44卷 / 08期
关键词：
burst-mode clock and data recovery; jitter reduction technique; gated oscillator; optical communications; passive optical network;
D O I：
10.1117/1.2012328
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
A clock and data recovery circuit using the clock jitter reduction technique is proposed for a 622-Mbit/s burst-mode data stream. The clock jitter reduction is achieved by controlling the clock duty cycle with the phase information of the recovered clock. The proposed clock recovery circuit, based on the gated oscillator, recovers a low-jitter output clock with up to 4090 consecutive zeros. (c) 2005 Society of Photo-Optical Instrumentation Engineers.
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页数：4
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