FPGA implementation of an interpolation processor for soft-decision decoding of Reed-Solomon codes

被引：3
|
作者：
Chen, Qinqin [1 ]
Wang, Zhongfeng [1 ]
Ma, Jun [2 ]
机构：
[1] Oregon State Univ, Sch EECS, Corvallis, OR 97331 USA
[2] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA
来源：
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 | 2007年
关键词：
D O I：
10.1109/ISCAS.2007.378513
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents an FPGA implementation of a high-speed interpolation processor for algebraic soft-decision decoding of Reed-Solomon codes. In the design, pipelining and parallel processing techniques are exploited to increase the decoding throughput In addition, different parts of the interpolation processor are properly scheduled to achieve maximum overlap in processing time for the computations occurring at adjacent iterations. Synthesis results show that the FPGA implementation of the interpolation architecture can achieve a throughput of 149Mbps, which is multiple times higher than conventional design.
引用
收藏
页码：2100 / +
页数：2
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