Verification of Initialization Sequences for Sequential Circuits

被引：0

作者：

Morkunas, K. ^{[1
]}

Seinauskas, R. ^{[1
]}

机构：

[1] Kaunas Univ Technol, Software Engn Dept, Studentu Str 50-406, LT-51368 Kaunas, Lithuania

来源：

ELEKTRONIKA IR ELEKTROTECHNIKA | 2011年 / 06期

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article suggests an approach for verification of initializing sequences. Such sequences were discovered using circuit emulating software prototypes. Software prototypes operate using bivalent logics (0 and 1), while hardware testing employs ternary logic (0, 1 and X). Experimental results show, that validation using ternary logic is too strict, labeling good initializing sequences as bad ones. Experimental results are based on ISCAS'89 benchmark. III. 1, bibl. 12, tabl. 3 (in English; abstracts in English and Lithuanian).

引用

页码：61 / 64

页数：4

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