Body-Bias Effect in SOI FinFET for Low-Power Applications: Gate Length Dependence

被引：0
|
作者：
Sachid, Angada B. [1 ]
Khandelwal, Sourabh [1 ]
Hu, Chenming [1 ]
机构：
[1] Univ Calif Berkeley, Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源：
PROCEEDINGS OF TECHNICAL PROGRAM - 2014 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | 2014年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
We study the gate length dependence of body-bias effect in SOI FinFETs. Using measurements and simulations we show that body-bias effect is enhanced as the gate length is decreased. We study the impact of channel doping and device geometry on body-bias effect.
引用
收藏
页数：2
相关论文
共 50 条
  • [41] 45nm gate length bulk/PD-SOI CMOS transistors with low gate leakage current for high speed and low power applications
    Yang, CK
    Chen, TF
    Liang, CS
    Chen, TJ
    Chang, TC
    Cheng, LW
    Lin, HS
    Li, G
    Wu, DY
    Chen, JK
    Chien, SC
    Sun, SW
    Cheek, J
    Michael, M
    Wu, D
    Fisher, P
    Wristers, D
    ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, : 415 - 418
  • [42] New SRAM design using body bias technique for low-power and high-speed applications
    Faraji, Rasoul
    Naji, Hamid Reza
    Rahimi-Nezhad, Majid
    Arabnejhad, Mohammad
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2014, 42 (11) : 1189 - 1202
  • [43] Fully silicided NiSi gate electrodes on HNON gate dielectrics for low-power applications
    Manabe, K
    Takahashi, K
    Ikarashi, T
    Morioka, A
    Watanabe, H
    Yoshihara, T
    Tatsumi, T
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (4B): : 2205 - 2209
  • [44] Fully depleted CMOS/SOI device design guidelines for low-power applications
    Banna, SR
    Chan, PCH
    Chan, MS
    Fung, SKH
    Ko, PK
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (04) : 754 - 761
  • [45] Quasi-Double Gate Mode for Sleep Transistors in UTBB FD SOI Low-Power High-Speed Applications
    Bol, David
    Kilchytska, Valeriya
    De Vos, Julien
    Andrieu, Francois
    Flandre, Denis
    IEEE INTERNATIONAL SOI CONFERENCE, 2012,
  • [46] Vertically integrated SOI circuits for low-power and high-performance applications
    Wei, LQ
    Zhang, RT
    Roy, K
    Chen, ZP
    Janes, DB
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (03) : 351 - 362
  • [47] Strained SOI technology for high-performance, low-power CMOS applications
    Takagi, S
    Mizuno, T
    Tezuka, T
    Sugiyama, N
    Numata, T
    Usuda, K
    Moriyama, Y
    Nakaharai, S
    Koga, J
    Tanabe, A
    Maeda, T
    2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS, 2003, 46 : 376 - +
  • [48] A Scalable Body Bias Optimization Method Toward Low-Power CGRAs
    Kojima, Takuya
    Okuhara, Hayate
    Kondo, Masaaki
    Amano, Hideharu
    IEEE MICRO, 2023, 43 (01) : 49 - 57
  • [49] Hall effect circuit for low-power applications
    Holmes, J.S.
    1996, (13):
  • [50] HIGH-SPEED AND LOW-POWER N(+)-P(+) DOUBLE-GATE SOI CMOS
    SUZUKI, K
    TANAKA, T
    TOSAKA, Y
    HORIE, H
    SUGII, T
    IEICE TRANSACTIONS ON ELECTRONICS, 1995, E78C (04) : 360 - 367
12345