New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

被引：39

作者：

Lillis, J ^{[1
]}

Cheng, CK ^{[1
]}

Lin, TTY ^{[1
]}

Ho, CY ^{[1
]}

机构：

[1] UNIV CALIF SAN DIEGO,CSE DEPT,LA JOLLA,CA 92093

来源：

33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996 | 1996年

关键词：

D O I：

10.1109/DAC.1996.545608

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：395 / 400

页数：6

共 38 条

[21] Computing the entire active area power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator
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Buurman, PHW
Jess, JAG
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (11) : 1424 - 1434
[22] Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning
Yan, J.-T., IEEE Circuits and Systems Society; Hiroshima University (Institute of Electrical and Electronics Engineers Inc.):
[23] Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning
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[24] Simultaneous wiring and buffer block planning with optimal wire-sizing for interconnect-driven floorplanning
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Lu, CH
Wu, CW
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS, 2004, : 469 - 472
[25] A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints
Tang, XP
Tian, RQ
Xiang, H
Wong, DF
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[26] New performance-driven FPGA routing algorithms
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Robins, G
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (12) : 1505 - 1517
[27] Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
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Wang, Jun-Jie
2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2021, : 1129 - 1134
[28] PERFORMANCE STUDY OF ROUTING AND ENERGY EFFICIENT TECHNIQUES ON WIRELESS BODY AREA NETWORK
Isabel, R. A.
Baburaj, E.
IIOAB JOURNAL, 2016, 7 : 247 - 254
[29] Delay performance of the new explicit loss notification TCP technique for wireless networks
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Jamalipour, A
GLOBECOM '01: IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, VOLS 1-6, 2001, : 3483 - 3487
[30] Performance driven multi-layer general area routing for PCB/MCM designs
Cong, J
Madden, PH
1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 356 - 361

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