A novel area-efficient binary adder

被引：0
|
作者：
Furber, SB [1 ]
Liu, J [1 ]
机构：
[1] Univ Manchester, Dept Comp Sci, Manchester M13 9PL, Lancs, England
来源：
CONFERENCE RECORD OF THE THIRTY-FOURTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS | 2000年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel circuit for binary addition based on a parallel-prefix carry structure is presented. This circuit uses a recoding of the conventional carry kill and generate terms to yield a number of improvements over previous designs. In particular; a single circuit produces both the carry signals and the Sum, Sum + 1 data that is required for a carry selection circuit, supporting a range of possible implementations all of which have high performance, regular layout and good area-efficiency. The simple design also leads to good power-efficiency. Binary adders based on this technique have been used in the ARM9TDMI the ARM Piccolo DSP coprocessor and the AMULET3 asynchronous ARM processor.
引用
收藏
页码：119 / 123
页数：3
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