FPGA implementation of programmable pulse mode neural network with on chip learning for signature application

被引：0
|
作者：
Krid, Mohamed [1 ]
Dammak, Alima [1 ]
Masmoudi, Dorra Sellami [1 ]
机构：
[1] Univ Sfax, Res Unit Intelligent Control Design & Optimisat C, Sfax Engn Sch, Sfax 3038, Tunisia
来源：
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an implementation of a signature recognition system based on pulse mode multilayer neural networks with on chip learning. Taking advantage of the compactness of the multiplierless solutions of pulse mode operations, we apply an architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can be adjusted without any added hardware cost. Good learning capability is obtained. As illustration, we consider a signature learning application. The corresponding design was implemented into an FPGA platform ( virtex H PRO XC2VP7).
引用
收藏
页码：942 / 945
页数：4
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