Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology

Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the half-select issue is resolved, meaning that no write-back operation is required. A folded-column structure is applied to the proposed 7T SRAM cell to reduce the read access time and energy consumption. To reduce the standby power, the proposed 7T SRAM cell uses only a single bit-line for both read and write operations. To achieve proper "1" writing operation with a single bit-line, a two-phase approach is proposed. Compared to the conventional 8T SRAM cell, the proposed 7T SRAM cell improves the read access time, energy, and standby power by 13%, 42%, and 23%, respectively, with a 3% smaller cell area.