A LOW POWER BIST SCHEME BASED ON BLOCK ENCODING

被引：0

作者：

Chen, Tian ^{[1
,2
]}

Zheng, Liuyang ^{[1
,2
]}

Wang, Wei ^{[1
,2
]}

Ren, Fuji ^{[1
,2
,3
]}

Zhang, Xishan ^{[1
]}

Chang, Hao ^{[1
]}

机构：

[1] Hefei Univ Technol, Sch Comp & Informat, Hefei 230009, Peoples R China

[2] Hefei Univ Technol, AnHui Prov Key Lab Affect Comp & Adv Intelligent, Hefei 230009, Peoples R China

[3] Univ Tokushima, Tokushima 7708506, Japan

来源：

2014 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT | 2014年

关键词：

LFSR reseeding; test data compression; low power test; test cube block; LFSR; DISSIPATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the development of integrated circuit manufacturing technology, low power test has become a focus of concern during testing fields. This paper proposes a new low power BIST (built-in self test) scheme based on block encoding which first exploit a block re-encoding method to optimize the test cube, and then a low power test based on LFSR (linear feedback shift register) reseeding is applied. According to the compatibility of flag, the scheme proposes a grouping algorithm based on flag to divide and reorder the test cubes in the test cube set. Experimental results show that the scheme not only obtain better test compression ratio and test data storage, but also reduce the test power consumption effectively.

引用

页数：7

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