A 5-GHz CMOS front-end circuit with low power, low noise and variable gain for WLAN applications

被引：3
|
作者：
Lin, M [1 ]
Li, YM [1 ]
Chen, HY [1 ]
机构：
[1] Tsing Hua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | 2003年
关键词：
D O I：
10.1109/VTSA.2003.1252608
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Incorporating the low-IF architecture, a 5-GHz WLAN receiver front-end chip is implemented in a 0.18mum CMOS technology. The chip contains a single-in differential-out low noise amplifier with 1.5dB noise figure (NF), 25dB; voltage gain and less than 13mW power consumption, a folded structure downconversion mixer with 9.9dB single side band noise figure (SSB NF), 13.7dB voltage gain and +2.7dBm IIP3, consuming 10mA current under a 2V supply voltage. The chip also has a 12dB gain adjustment through a VGA cell placed in parallel with LNA's input.
引用
收藏
页码：280 / 283
页数：4
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