A 1-V 5-GHz CMOS multiple magnetic feedback receiver front-end

被引：3
|
作者：
Vitzilaios, Georgios [1 ]
Papananos, Yannis [1 ]
Theodoratos, Gerasimos [1 ]
机构：
[1] Natl Tech Univ Athens, Dept Elect & Elect Engn, GR-15773 Athens, Greece
来源：
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2008年 / 56卷 / 06期
关键词：
CMOS analog circuits; linearization techniques; low-noise amplifier (LNA); mixer design; receiver topology;
D O I：
10.1109/TMTT.2008.921752
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for. optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBM's 0.13-mu m CMOS technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of +0.1 dBm.
引用
收藏
页码：1338 / 1348
页数：11
相关论文
共 50 条
  • [1] A 5-GHz highly integrated receiver front-end
    Ragonese, Egidio
    Italia, Alessandro
    Palmisano, Giuseppe
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2007, 53 (01) : 3 - 7
  • [2] A 5-GHz highly integrated receiver front-end
    Egidio Ragonese
    Alessandro Italia
    Giuseppe Palmisano
    Analog Integrated Circuits and Signal Processing, 2007, 53 : 3 - 7
  • [3] A 5-GHz CMOS wireless LAN receiver front end
    Samavati, H
    Rategh, HR
    Lee, TH
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (05) : 765 - 772
  • [4] A 1 V 1.1 GHz CMOS integrated receiver front-end
    Cheng, WC
    Chan, CF
    Pun, KP
    Choy, CS
    PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY, 2004, : 325 - 328
  • [5] 5-GHz CMOS radio transceiver front-end chipset
    Liu, TP
    Westerwick, E
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (12) : 1927 - 1933
  • [6] A transformer-based receiver front-end for 5-GHz WLANs
    Ragonese, Egidio
    Italia, Alessandro
    Seminara, Maria Francesca
    Palmisano, Giuseppe
    2006 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2006, : 467 - +
  • [7] A transfonner-based receiver front-end for 5-GHz WLANs
    Ragonese, Egidio
    Italia, Alessandro
    Seminara, Maria Francesca
    Palmisano, Giuseppe
    2006 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, 2006, : 417 - 420
  • [8] A 1-V, 5.5-GHz, CMOS LNA with multiple magnetic feedback
    Vitzilaios, Georgios
    Papananos, Yannis
    Theodoratos, Gerasimos
    Vasilopoulos, Athanasios
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (09) : 971 - 975
  • [9] Sub-nW 5-GHz receiver front-end circuit design
    Hsu, Tatao
    Liu, Yen-Lin
    Yen, Shu-Hui
    Kuo, Chien-Nan
    2007 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, DIGEST OF PAPERS, 2007, : 205 - +
  • [10] A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator
    Wu, CY
    Chou, CY
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (03) : 519 - 521
12345