An Efficient Approch to VLSI Circuit Partitioning using Evolutionary Algorithms

被引：2

作者：

Sangwan, Dhiraj ^{[1
]}

Verma, Seema ^{[2
]}

Kumar, Rajesh ^{[3
]}

机构：

[1] CSIR CEERI, Pilani, Rajasthan, India

[2] Banasthali Vidyapeeth, ECE Dept, Vanasthali, Rajasthan, India

[3] MNIT, ECE Dept, Jaipur, Rajasthan, India

来源：

2014 6TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS | 2014年

关键词：

Algorithm; Evolutionary Algorithm; VLSI; Circuit Partitioning; Kernighan Lin; Fiduccia Mattheyses Algorithm; optimization; Simulated Annealing; Genetic Algorithm; cut-size;

D O I：

10.1109/CICN.2014.195

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Circuit Partitioning generally formulated as graph partitioning problem is an important step in physical design of circuits. The use of Evolutionary techniques is increasingly used to solve NP complete problems i.e. applications for logic minimization and simulation heuristics. This paper explores the evolutionary approach of genetic algorithm and propose a hybrid technique involving the strengths of the existing techniques resulting in a better partitioning and placement of circuits. It can further be extended to the Hardware/Software boundary of algorithms and can be applied to real world physical design problems.

引用

页码：925 / 929

页数：5

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