Improved Analog Operation of Junctionless Nanowire Transistors Using Back Bias

被引:0
|
作者
Trevisoli, R. [1 ]
Doria, R. T. [1 ]
de Souza, M. [1 ]
Pavanello, M. A. [1 ]
机构
[1] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo, Brazil
关键词
Junctionless Transistors; Substrate Bias; Analog Operation;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This work reports, for the first time, an analysis of substrate bias on the analog parameters of Junctionless Nanowire Transistors operating as single transistor amplifiers through experimental and simulated data. The study is performed in terms of output conductance, transconductance, open loop voltage gain and transconductance to the drain current ratio. It has been shown that the substrate bias can affect significantly the performance of junctionless devices, such that the positive back bias can reduce the output conductance and improve the voltage gain.
引用
收藏
页码:265 / 268
页数:4
相关论文
共 50 条
  • [31] Cryogenic Characteristics of Ge channel Junctionless Nanowire Transistors
    Sun, Chuanchuan
    Liang, Renrong
    Xiao, Lei
    Liu, Libin
    Xu, Jun
    Wang, Jing
    2018 IEEE 2ND ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2018), 2018, : 286 - 288
  • [32] Mobility improvement in nanowire junctionless transistors by uniaxial strain
    Raskin, Jean-Pierre
    Colinge, Jean-Pierre
    Ferain, Isabelle
    Kranti, Abhinav
    Lee, Chi-Woo
    Akhavan, Nima Dehdashti
    Yan, Ran
    Razavi, Pedram
    Yu, Ran
    APPLIED PHYSICS LETTERS, 2010, 97 (04)
  • [33] Microscopic simulation of RF noise in junctionless nanowire transistors
    Maziar Noei
    Christoph Jungemann
    Journal of Computational Electronics, 2018, 17 : 986 - 993
  • [34] Electrical Characterization and Parameter Extraction of Junctionless Nanowire Transistors
    Rudenko, Tamara
    Barraud, Sylvain
    Georgiev, Yordan M.
    Lysenko, Vladimir
    Nazarov, Alexey
    JOURNAL OF NANO RESEARCH, 2016, 39 : 17 - +
  • [35] Electrostatics and Ballistic Transport Studies in Junctionless Nanowire Transistors
    Yu, T-H
    Hsu, Ethan
    Liu, C-W
    Colinge, J-P
    Sheu, Y-M
    Wu, Jeff
    Diaz, C. H.
    2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013), 2013, : 85 - 88
  • [36] Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors
    Pavanello, Marcelo A.
    Ribeiro, Thales A.
    Cerdeira, Antonio
    Avila-Herrera, Fernando
    2021 IEEE LATIN AMERICA ELECTRON DEVICES CONFERENCE (LAEDC), 2021,
  • [37] Physical Insights on the Dynamic Response of Junctionless Nanowire Transistors
    Doria, Rodrigo T.
    Trevisoli, Renan
    de Souza, Michelly
    Pavanello, Marcelo A.
    2016 31ST SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), 2016,
  • [38] Quasi-Static Analytical Model for the Dynamic Operation of Triple-Gate Junctionless Nanowire Transistors
    Trevisoli, R.
    Doria, R. T.
    de Souza, M.
    Pavanello, M. A.
    2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2015,
  • [39] Impact of series resistance on the operation of junctionless transistors
    Jeon, Dae-Young
    Park, So Jeong
    Mouis, Mireille
    Barraud, Sylvain
    Kim, Gyu-Tae
    Ghibaudo, Gerard
    SOLID-STATE ELECTRONICS, 2017, 129 : 103 - 107
  • [40] Trap studies in silicon nanowire junctionless transistors using low-frequency noise
    Opondo, Noah
    Ramadurgam, Sarath
    Yang, Chen
    Mohammadi, Saeed
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2016, 34 (01):