A novel improvement technique for high-level test synthesis

被引：0

作者：

Safari, S ^{[1
]}

Esmaeilzadeh, H ^{[1
]}

Jahangir, AH ^{[1
]}

机构：

[1] Sharif Univ Technol, CE Dept, Tehran, Iran

来源：

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS | 2003年

关键词：

HLS; register allocation; incompatible variables; conflict graph; weighted graph coloring; simulated annealing;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs. reduced design iteration, and significant improved fault coverage. In this paper, we present a novel register allocation method, which is based on weighted graph coloring algorithm, targeting testability improvement for digital circuits. The topics covered in this paper include an overview of HLS and testability parameters, our testability model and experimental results.

引用

页码：609 / 612

页数：4

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