The recursive grid layout scheme for VLSI layout of hierarchical networks

被引：5

作者：

Yeh, CH ^{[1
]}

Parhami, B ^{[1
]}

Varvarigos, EA ^{[1
]}

机构：

[1] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA

来源：

IPPS/SPDP 1999: 13TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM & 10TH SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/IPPS.1999.760514

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose the recursive grid layout scheme for deriving efficient layouts of a variety of hierarchical networks and computing upper bounds on the VLSI area of general hierarchical networks. In particular; we construct optimal VLSI layouts for butterfly networks, generalized hypercubes, and star graphs that have areas within a factor of 1 + o(I) from their lower bounds. We also derive efficient layouts for a number of other important networks, suck as cube-connected cycles (CCC) and hypernets, which are the best results reported for these networks thus far.

引用

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页码：441 / 445

页数：5

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