共 50 条
- [1] A METHODOLOGY FOR CUSTOM VLSI LAYOUT IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1983, 30 (06): : 358 - 364
- [6] GENERAL HIERARCHICAL AUTOMATIC LAYOUT OF CUSTOM VLSI CIRCUIT MASKS JOURNAL OF DESIGN AUTOMATION & FAULT-TOLERANT COMPUTING, 1979, 3 (01): : 41 - 58
- [7] GENERAL HIERARCHICAL AUTOMATIC LAYOUT OF CUSTOM VLSI CIRCUIT MASKS. Journal of Design Automation & Fault-Tolerant Computing, 1979, 3 : 41 - 58
- [8] Modified Standard Cell Methodology for VLSI Layout Compaction 2012 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING, COMPUTING SCIENCE AND AUTOMATIC CONTROL (CCE), 2012,
- [9] DESIGN METHODOLOGY AND CAD TOOLS FOR FULL-CUSTOM VLSI DESIGN ELECTRICAL COMMUNICATION, 1986, 60 (3-4): : 196 - 206