A METHODOLOGY FOR CUSTOM VLSI LAYOUT

被引：0
|
作者：
BREUER, MA
KUMAR, A
机构：
来源：
IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS | 1983年 / 13卷 / 04期
关键词：
D O I：
10.1109/TSMC.1983.6313133
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
下载
收藏
页码：470 / 475
页数：6
相关论文
共 50 条
  • [41] MASHER - AN AUTOMATIC VLSI LAYOUT SYSTEM
    PETERSON, JC
    SMITH, KF
    INTEGRATION-THE VLSI JOURNAL, 1986, 4 (01) : 3 - 33
  • [42] Rapid layout synthesis for analog VLSI
    Walczowski, LT
    Waller, WAJ
    Nalbantis, D
    Shi, K
    ICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2, 1996, : 378 - 381
  • [43] VLSI layout and packaging of butterfly networks
    Yeh, Chi-Hsiang
    Parhami, Behrooz
    Varvarigos, E.A.
    Lee, H.
    Annual ACM Symposium on Parallel Algorithms and Architectures, 2000, : 196 - 205
  • [44] AUTOMATIC LAYOUT SYSTEM FOR VLSI.
    Porter, Edwin H.
    1979, : 9 - 14
  • [45] Multilayer VLSI layout for interconnection networks
    Yeh, CH
    Varvarigos, EA
    Parhami, B
    2000 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, PROCEEDINGS, 2000, : 33 - 40
  • [46] GEOMETRIC APPROACH TO VLSI LAYOUT COMPACTION
    XIONG, XM
    KUH, ES
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 1990, 18 (04) : 411 - 430
  • [47] Layout techniques for VLSI yield enhancement
    Chen, Z
    Zhang, LX
    ADVANCES IN MICROELECTRONIC DEVICE TECHNOLOGY, 2001, 4600 : 140 - 147
  • [48] RESEARCH IN DESIGN AUTOMATION FOR VLSI LAYOUT
    KOZAWA, T
    TERAI, H
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (05): : 43 - 53
  • [49] Power optimization in VLSI layout: A survey
    Pedram, M
    Vaishnav, H
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1997, 15 (03): : 221 - 232
  • [50] Hierarchical VLSI layout circuit extraction
    Zeng, Xian-Qiang
    Chen, Hou-Peng
    0
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design & Computer Graphics, 1998, 10 (Suppl): : 101 - 105
12345