Design and Analysis of Low Power, Area Efficient Skip Logic for CSKA Circuit in Arithmetic Unit

被引：0

作者：

Vijayakumar, S. ^{[1
]}

Jayaprakasan, V. ^{[1
]}

Korah, Reeba ^{[2
]}

机构：

[1] SITAMS Autonomous, Dept ECE, Chittoor 517127, Andhra Pradesh, India

[2] Alliance Univ, Alliance Coll Engg & Design, Bangalore 562106, Karnataka, India

来源：

2018 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS) | 2018年

关键词：

Carry Skip Adder; CSKA; GDI MUX; Low Power; Skip Logic; ALU; CARRY-LOOKAHEAD ADDERS; DELAY OPTIMIZATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Processor cores of all the digital things have CPU with ALU as main block as a fact. Adder is the fundamental arithmetic component which performs considerable work. This article discusses the design, analysis of power optimized and area reduced Carry Skip Adder (CSKA). Area and Power are minimized with the help Hybrid GDI kind of MUX structure in skip logic of CSKA. The proposed one requires 39% low power consumption at the expense of 22% more delay than Transmission Gate (TG) based structure for skip logic. It's area in terms of cell count is negligibly smaller than CMOS MUX.

引用

页码：162 / 166

页数：5

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