Design and Analysis of Low Power, Area Efficient Skip Logic for CSKA Circuit in Arithmetic Unit

被引：0

作者：

Vijayakumar, S. ^{[1
]}

Jayaprakasan, V. ^{[1
]}

Korah, Reeba ^{[2
]}

机构：

[1] SITAMS Autonomous, Dept ECE, Chittoor 517127, Andhra Pradesh, India

[2] Alliance Univ, Alliance Coll Engg & Design, Bangalore 562106, Karnataka, India

来源：

2018 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS) | 2018年

关键词：

Carry Skip Adder; CSKA; GDI MUX; Low Power; Skip Logic; ALU; CARRY-LOOKAHEAD ADDERS; DELAY OPTIMIZATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Processor cores of all the digital things have CPU with ALU as main block as a fact. Adder is the fundamental arithmetic component which performs considerable work. This article discusses the design, analysis of power optimized and area reduced Carry Skip Adder (CSKA). Area and Power are minimized with the help Hybrid GDI kind of MUX structure in skip logic of CSKA. The proposed one requires 39% low power consumption at the expense of 22% more delay than Transmission Gate (TG) based structure for skip logic. It's area in terms of cell count is negligibly smaller than CMOS MUX.

引用

页码：162 / 166

页数：5

共 50 条

[31] Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic
Lu, Chao
Banerjee, Utsav
Basu, Kanad
[J]. 2022 IEEE 40TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2022), 2022, : 109 - 116
[32] Efficient Temporal Arithmetic Logic Design for Superconducting RSFQ Logic
Vasudevan, Dilip
Michelogiannakis, George
[J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2023, 33 (05)
[33] A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit
Barla, Prashanth
Joshi, Vinod Kumar
Bhat, Somashekara
[J]. IEEE ACCESS, 2020, 8 : 6876 - 6889
[34] A Design of Fault Tolerant Reversible Arithmetic Logic Unit
Safari, Parisa
Haghparast, Majid
Azari, Asgar
[J]. LIFE SCIENCE JOURNAL-ACTA ZHENGZHOU UNIVERSITY OVERSEAS EDITION, 2012, 9 (03): : 643 - 646
[35] Low Area Elliptic Curve Arithmetic Unit
Fournaris, Apostolos P.
Koufopavlou, Odysseas
[J]. ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 1397 - +
[36] REVERSIBLE/QUANTUM TERNARY ARITHMETIC LOGIC UNIT DESIGN
Deibuk, Vitaly
[J]. INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2016, 12 (05): : 1523 - 1533
[37] Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU)
Gopal, Lenin
Mahayadin, Nor Syahira Mohd
Chowdhury, Adib Kabir
Gopalai, Alpha Agape
Singh, Ashutosh Kumar
[J]. 2014 INTERNATIONAL CONFERENCE ON COMPUTER, COMMUNICATIONS, AND CONTROL TECHNOLOGY (I4CT), 2014, : 289 - 293
[38] Correction to: Novel Design for Reversible Arithmetic Logic Unit
Rigui Zhou
Yancheng Li
Manqun Zhang
BenQiong Hu
[J]. International Journal of Theoretical Physics, 2018, 57 : 300 - 300
[39] Complement Based Logic Design (CBLD) for Area and Power Efficiency of Arithmetic Building Blocks
Patil, Nikhil
Geddamuri, Teja
Nikoubin, Tooraj
[J]. 7TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT 2016), 2016,
[40] Design & Implementation of Area Efficient Low Power High Speed MAC Unit using FPGA
Pawar, Roshani
Shriramwar, S. S.
[J]. 2017 IEEE INTERNATIONAL CONFERENCE ON POWER, CONTROL, SIGNALS AND INSTRUMENTATION ENGINEERING (ICPCSI), 2017, : 2683 - 2687

← 1 2 3 4 5 →